1. Field of the Invention
The present invention relates to a process for defining a chalcogenide material layer, in particular in a process for manufacturing phase change memory cells.
2. Description of the Related Art
As is known, phase change memory cells utilize a class of materials that have the unique property of being reversibly switchable from one phase to another with measurable distinct electrical properties associated with each phase. For example, these materials may change between an amorphous disordered phase and a crystalline, or polycrystalline, ordered phase. A material property that may change and provide a signature for each phase is the material resistivity, which is considerably different in the two states. Thus a thin film of chalcogenic material may be employed as a programmable resistor, switching between a high and a low resistance condition.
The phase of a chalcogenide material may be modified by passing electrical currents of suitable values for preset times. Furthermore, the state of the chalcogenic material may be read by applying a sufficiently small voltage (or current) so as not to cause an appreciable heating and measuring the current passing through it (or voltage across it). Since the current is proportional to the conductance (or voltage is proportional to the resistance) of the chalcogenic material, it is possible to discriminate between the two phases.
Thus, the use of chalcogenide materials has been already proposed for making phase change memory cells.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase change memory cells. The currently most promising chalcogenide is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5), also called GST, which is currently widely used for storing information in overwritable disks.
The basic structure of a PCM element 1 is shown in FIG. 1 and comprises a first electrode 2 of resistive type, forming a heater; a programmable element 3, in contact with the first electrode 2; and a second electrode 5 of a metal material, for example AlCu. A barrier layer 4, for example of Ti/TiN, is generally arranged between the programmable element 3 and the second electrode 5.
Definition of the programmable element 3, barrier layer 4 and the second electrode 5 gives rise to some difficulties.
Presently, chalcogenic materials are mainly used in microelectronic field to improve the definition of structures in the substrate. For example, chalcogenide layers are used in addition to lithographic masks and act directly as masking layers since they have particular properties with regards to photosensitivity and photolithographic development. In the alternative, the ability of the chalcogenic material is exploited to form compounds that are particularly reactive with the substrate to be defined, both with regards to plasma etching and etching in aqueous e/o organic solution. The multilayer obtained by depositing the chalcogenic material on the substrate to be defined is exposed to a radiation through a standard lithographic mask, which defines only the areas where the substrate is to be exposed. The reaction between the remaining chalcogenic material and the substrate forms a third component that is more reactive to a wet or plasma etching. The chemicals used for plasma etching include fluorinated gases, such as CF4, CHF3, C2F8, CClF3 or mixtures of O2, N2, and Ar.
As said, in all cases cited in literature the chalcogenic layer is used to define the underlying substrate and not as the layer to be defined to form an active region. Furthermore, the chemicals used (as said, based on fluorinated gases or mixtures of O2, N2, and Ar) are not compatible with metal layers of AlCu, Ti and TiN. Although the fluorinated gases are able to etch the AlCu layer, the reaction speed is low. Moreover, from tests made by the applicant, it was noted that the structures of AlCu, after being exposed to a CF4 plasma for some tens of seconds, present holes in the lower part, due to an overetching by fluorine. A CF4 plasma also etches TiN heavily on the upper part of the structure.
Thus, presently no satisfying etching is available for the definition of GST layers used in microelectronics and thus forming active portions of an integrated semiconductor device.